Precoding Schemes for Millimeter Wave Massive MIMO Systems

In an effort to cut high cost and power consumption of radio frequency (RF) chains, millimeter wave (mmWave) multiple input multiple output (MIMO) deploys hybrid architecture in which precoding is implemented as a combination of digital precoding and analog precoding, accomplished by using a smaller number of RF chains and a network of phase shifters respectively. The mmWave MIMO, which usually suffers from blockages, needs to be supported by Reconfigurable Intelligent Surface (RIS) to make communication possible. Along with the hybrid precoding in mmWave MIMO, the passive precoding of Reconfigurable Intelligent Surface (RIS) is investigated in a downlink RIS-assisted mmWave MIMO. The hybrid precoding and passive precoding are challenged by the unit modulus constraints on the elements of analog precoding matrix and passive precoding vector. The coupling of analog and digital precoders further complicates the hybrid precoding. One of the approaches taken in proposed hybrid precoding algorithms is the use of alternating optimization in which analog precoder and digital precoder are optimized alternately keeping the other fixed. Analog precoder is determined by solving a semidefinite programming problem, and from the unconstrained least squares solution during each iteration. In another approach taken in the proposed methods, the hybrid precoding is split into separate analog and digital precoding subproblems. The analog precoding subproblems are simplified using some approximations, and solved by using iterative power method and employing a truncated singular value decomposition method in two different hybrid precoding algorithms. In the prooposed codebook-based precoder, analog precoder is constructed by choosing precoding vectors from a codebook to maximize signal-to-leakage-and-noise ratio (SLNR). The passive precoding at the RIS in a single user MIMO is designed to minimize mean square error between the transmit signal and the estimate of received signal by using an iterative algorithm that solves the joint optimization problem of precoding, passive precoding and combiner. The problem of designing energy efficient RIS is solved by maximizing energy efficiency which is a joint optimization problem involving precoder, passive precoding matrix and power allocation matrix. The proposed hybrid precoding and passive precoding algorithms deliver very good performances and prove to be computationally efficient

Automatic Rtl-To-Formal Code Converter For Ip Security Formal Verification

The wide usage of hardware intellectual property (IP) cores from untrusted vendors has raised security concerns in the integrated circuit (IC) industry. Existing testing methods are designed to validate the functionality of the hardware IP cores. These methods often fall short in detecting unspecified (often malicious) logic. Formal methods like Proof-Carrying Hardware (PCH), on the other hand, can help eliminate hardware Trojans and/or design backdoors by formally proving security properties on soft IP cores despite the high proof development cost. One of the causes to the high cost is the manual conversion of the hardware design from RTL code to a domain-specific language prior to verification. To mitigate this issue and to lower the overall cost of PCH framework, we propose an automatic code converter for translating VHDL to Formal-HDL, a domain specific language for representing hardware designs in Coq language. Our code converter provides support to wide variety of hardware designs. Towards the goal of speeding up the verification procedure in our PCH framework, the code converter is the important first step. The applicability of the tool is demonstrated by converting soft IP cores of AES to its Coq equivalent code

Scalable Soc Trust Verification Using Integrated Theorem Proving And Model Checking

The wide usage of hardware Intellectual Property (IP) cores and software programs from untrusted vendors have raised security concerns for system designers. Existing solutions for detecting and preventing software attacks do not usually consider the presence of malicious logic in hardware. Similarly, hardware solutions for detecting Trojans and/or design backdoors do not consider the software running on it. Formal methods provide powerful solutions in detecting malicious behaviors in both hardware and software. However, they suffer from scalability issues and cannot be easily used for large-scale computer systems. To alleviate the scalability challenge, we propose a new integrated formal verification framework to evaluate the trust of computer systems constructed from untrusted third-party software and hardware resources. This framework combines an automated model checker with an interactive theorem prover for proving system-level security properties. We evaluate a vulnerable program executed on a bare metal LEON3 SPARC V8 processor and prove system security with considerable reduction in effort. Our method systematically reduces the effort required for verifying the program running on the System-on-Chip (SoC) compared to traditional interactive theorem proving methods

Pre-Silicon Security Verification And Validation: A Formal Perspective

Reusable hardware Intellectual Property (IP) based System-on-ChIP (SoC) design has emerged as a pervasive design practice in the industry today. The possibility of hardware Trojans and/or design backdoors hiding in the IP cores has raised security concerns. As existing functional testing methods fall short in detecting unspecified (often malicious) logic, formal methods have emerged as an alternative for validation of trustworthiness of IP cores. Toward this direction, we discuss two main categories of formal methods used in hardware trust evaluation: theorem proving and equivalence checking. Specifically, proof-carrying hardware (PCH) and its applications are introduced in detail, in which we demonstrate the use of theorem proving methods for providing high-level protection of IP cores. We also outline the use of symbolic algebra in equivalence checking, to ensure that the hardware implementation is equivalent to its design specification, thus leaving little space for malicious logic insertion